Grants8 | The most comprehensive grants search on the web

Grant Analysis

Core Objective: To establish a sustainable accelerator providing access to state-of-the-art sSOI technology and manufacturing capabilities, fostering the development and industrial scaling of 7nm FD-SOI technology, and strengthening Europe's leadership in critical semiconductor markets.
Target Recipient Types: European stakeholders including businesses, research organizations, and educational institutions with expertise in semiconductor technology and manufacturing.
SECTOR-SPECIFIC
Geographic Scope: European Union member states.
Key Filtering Criteria: Focus on sSOI substrate development, 7nm FD-SOI technology, industrial-scale wafer production, intellectual property creation in semiconductors, and collaboration within the European semiconductor ecosystem.
Grant Frequency and Program Context: This is a specific call under the Chips Joint Undertaking (Chips JU) framework, likely a one-time opportunity under this specific topic ID, focusing on a critical aspect of Europe's semiconductor strategy.

Budget Range per Grant: Minimum 1,000,000 EUR to a maximum of 30,000,000 EUR.
Currency: EUR.
Total Topic Budget: 30,000,000 EUR for the year 2025.
Eligible Costs: Details on eligible costs are expected to be in the referenced 'EU Grants AGA — Annotated Model Grant Agreement' and 'EU Financial Regulation 2024/2509'. These documents typically define categories of direct and indirect costs.
Co-financing Requirements: Not explicitly stated in the provided text, but commonly required for EU grants. Applicants should refer to the 'Legal and financial set-up of the grants' and the 'Annotated Model Grant Agreement' for details.
Payment Mechanisms: The grant type is 'DIGITAL Action Grant Budget-Based', suggesting payments will be linked to project budget and progress, with mechanisms detailed in the grant agreement.
Financial Reporting: Subject to 'EU Financial Regulation 2024/2509', implying strict financial reporting and potential audit requirements, detailed in the 'Legal and financial set-up of the grants'.
Funding Rate: Not specified.

Organizational Type & Geographic Location

Eligible organizations include 'all European stakeholders'. This broadly covers:
- Industrial entities (e.g., ENTERPRISE, SME) involved in semiconductor manufacturing.
- Research organizations and UNIVERSITY entities with relevant technical expertise.
Must be based in a country eligible for EU funding, implying European Union member states.

Capacity & Track Record

Must demonstrate financial and operational capacity to undertake a project of significant scale (up to 30,000,000 EUR).
Required to have the capability to 'bring sSOI substrates to industrial scale', suggesting a strong track record in semiconductor R&D and manufacturing.

General Conditions

Adherence to specified page limits and layout for proposals as described in the Chips JU Call page documents.
Compliance with 'Eligible Countries' (not detailed in this document but generally EU member states for such calls).
Compliance with 'Other Eligible Conditions' (not detailed here).
Adherence to 'Financial and operational capacity and exclusion' criteria, meaning organizations must be financially sound and not be subject to exclusion grounds.

Application Timeline & Submission

Submission Deadline: 2025-11-20 00:00:00+00.
Application Opening Date: 2025-07-08.
Submission Procedure: Single-stage submission process.
Submission Platform: Proposals must be submitted via the 'Electronic Submission Service' on the Funding & Tenders Portal.

Required Documentation & Materials

Application Form Template Part B (content of the proposal).
National funding table template.
Ownership declaration template.
Additional reference documents available on the Chips JU Call page, including:
- Guide for Applicants.
- Evaluation form.

Application Support

For call-specific inquiries: contact 'calls@chips-ju.europa.eu'.
For general technical issues (e.g., forgotten passwords, access rights): contact the 'IT Helpdesk'.
For guidance on the portal processes: consult the 'Funding & Tenders Portal Online Manual'.

Project Impact & Outcomes

Creation of a sustainable accelerator that is open to all European stakeholders, providing access to state-of-the-art sSOI technology and manufacturing capabilities.
Development and standardization of Process Design Kits (PDKs) based on validated sSOI substrate data, enabling optimization of system-level architectures for next-generation applications.
Support for the transition to 7nm FD-SOI technology, ensuring readiness for high-volume manufacturing by 2030.
Expansion of sSOI substrates capabilities to industrial-scale wafer production, with emphasis on low defect densities and improved manufacturing yields meeting advanced semiconductor fabrication standards.
Contribution to the creation of intellectual property and strengthening Europe's production capacity in sSOI technologies, supporting European leadership in critical semiconductor markets.
Complementarity and synergies with the FD-SOI pilot line and other Chips JU pilot lines, enhancing overall innovation capacity and technological leadership in semiconductor technologies.

Technical Scope & Quality

Development of industrial-grade sSOI substrates focusing on achieving low defect density for high-performance FD-SOI devices at the 7nm node.
Refinement of strain engineering techniques, particularly to introduce a uniform global strain.
Ensuring compatibility with existing semiconductor manufacturing processes.
Improvement of epitaxial growth, wafer bonding, and defect reduction techniques to meet advanced FD-SOI production requirements.

Collaboration & Skill Development

Promotion of collaboration across the semiconductor ecosystem, including other pilot lines, design platforms, and competence centers.
Provision of comprehensive training programs and skill development initiatives to equip European technologists and engineers with expertise in sSOI substrate integration and advanced semiconductor manufacturing.

Regulatory & Financial Compliance

Regulatory Framework: Compliance with 'DEP Regulation 2021/964'.
Financial Regulations: Adherence to 'EU Financial Regulation 2024/2509' for financial management and reporting.

Data Protection & Ethical Standards

Data Privacy: Compliance with the 'Funding & Tenders Portal Privacy Statement'.
Ethical Standards: Implicitly required for all EU-funded projects; specific ethical guidelines would be detailed in the grant agreement.

Intellectual Property (IP) & Technology Focus

IP Policies: Project aims to 'drive the creation of intellectual property', indicating specific IP policies will apply, likely favoring European ownership and exploitation of results.
Technical Specifications: Projects must focus on 'state-of-the-art sSOI technology', '7nm FD-SOI technology', 'strain engineering techniques', 'epitaxial growth', 'wafer bonding', and 'defect reduction techniques' for semiconductor manufacturing.

Strategic & Collaborative Requirements

Collaboration: Strong emphasis on 'collaborative development' and 'synergies with other Chips JU pilot lines', and 'collaboration across the semiconductor ecosystem'. While not explicitly stated as a mandatory consortium, partnership is highly encouraged and likely necessary for success.
Capacity Building: Projects are expected to 'provide comprehensive training programs and skill development initiatives' to bolster European expertise.
Risk Management: Implicitly expected through 'improved manufacturing yields' and 'low defect densities' targets.