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Grant Analysis

Purpose & Target

This grant aims to coordinate and support joint research and innovation (R&I) activities between the European Union and Japan in the critical field of semiconductors. The core objective is to improve coherence in life cycle assessment (LCA) of semiconductor manufacturing, foster talent exchange, and strengthen the security of the semiconductor supply chain. - Target recipient types: Research institutions, universities, and companies (including SMEs and larger enterprises) involved in the semiconductor value chain. - SECTOR-SPECIFIC: Yes, focused on semiconductors and related digital technologies. - Geographic scope: Organizations based in EU Member States and Japan. - Key filtering criteria: Projects must involve EU-Japan collaboration, address semiconductor R&I, and focus on coordination, networking, or supply chain stability. - Grant frequency: This is a specific call within the multi-annual Multi Annual Work Programme of Chips JU.

Financial Structure

The minimum grant contribution per project is EUR 500,000.0.
The maximum grant contribution per project is EUR 1,000,000.0.
The grant type is identified as a 'HORIZON Action Grant Budget-Based'.
Information regarding eligible and ineligible costs, as well as financial reporting requirements, is described in Appendix 5 of the Multi Annual Work Programme of Chips JU and Annex G of the Work Programme General Annexes (details not provided in source).

Eligibility Requirements

Organizational Type and Status

Applicants must be legal entities.
Eligible organization types are implied to include universities, research institutions, and companies (SMEs and larger enterprises) engaged in semiconductor R&I and manufacturing.
Eligibility conditions regarding financial and operational capacity are described in Annex C of the Work Programme General Annexes and Appendix 5 of the Multi Annual Work Programme of Chips JU (details not provided in source).

Geographic Location

Organizations must be established in an EU Member State or Japan.

Other Specific Conditions

Other specific eligibility conditions are outlined in Appendix 5 of the Multi Annual Work Programme of Chips JU (details not provided in source).

Application Process

Application Submission

The application form specific to this call is available in the online Submission System.
Proposals must be submitted via the Electronic Submission Service.
Proposal page limits and layout are described in Part B of the Application Form.

Submission Deadline

The submission session for this call is available from 2025-07-08.
The final deadline for proposal submission is 2025-09-17 00:00:00+00.

Evaluation and Award Timeline

The indicative timeline for evaluation and grant agreement is detailed in Appendix 5 of the Multi Annual Work Programme of Chips JU (details not provided in source).

Application Support

General guidance is available through the HE Programme Guide, Model Grant Agreements (MGA), and the Funding & Tenders Portal Online Manual.
For call-specific inquiries, applicants can contact Calls@chips-ju.europa.eu.
A partner search functionality is available on the Funding & Tenders Portal to assist in finding consortium partners.

Evaluation Criteria

Project Quality and Strategic Alignment

Relevance and quality of proposed coordination and support actions in fostering EU-Japan R&I collaboration on semiconductors.
Contribution to improving coherence in life cycle assessment (LCA) of semiconductor manufacturing processes.
Effectiveness of plans for researcher exchange and joint R&I activities.
Potential for preparing future joint EU-Japan R&I collaboration topics in semiconductors.
Opportunities to finance talent exchanges between R&D or production sites in both regions.
Fostering increased cooperation with appropriate research institutions in Japan on the development, deployment, and commercialisation of digital technologies.
Support for joint activities of companies in the semiconductor value chain to improve security of supply for chips.

Implementation and Impact

Quality and feasibility of proposed networks, conferences, workshops, and other actions to support semiconductor joint EU-Japan R&I activities.
Effectiveness of efforts to connect EU and Japanese companies in the semiconductor value chain for information exchange and supply chain stability.
Plans for increased networking and collaboration of stakeholders from the EU and Japan.
Robustness of strategies to engage relevant stakeholders from both EU and Japan through regional/international workshops and communication/dissemination actions.

General Evaluation

Award criteria, scoring, and thresholds are detailed in Appendix 5 of the Multi Annual Work Programme of Chips JU (specifics not provided in source).

Compliance & Special Requirements

Regulatory Compliance

The legal and financial setup of the grants is described in Appendix 5 of the Multi Annual Work Programme of Chips JU and Annex G of the Work Programme General Annexes.
Projects must comply with the EU Financial Regulation 2024/2509.
Adherence to rules for Legal Entity Validation, LEAR (Legal Entity Appointed Representative) Appointment, and Financial Capacity Assessment is required.

Technical and Environmental Focus

A key expected outcome is to improve coherence in Life Cycle Assessment (LCA) of semiconductor manufacturing processes, potentially leading to the development of a reference database for LCA or Green House Gas (GHG) emissions.

Collaboration and Strategic Importance

This grant is a Coordination and Support Action (CSA) specifically designed to foster and support robust collaboration between EU and Japanese entities.
Emphasis on addressing current needs, future requirements, and stimulating long-term cooperation in the semiconductor sector.
The initiative supports the strategic objective of improving security of supply for chips within the semiconductor value chain.
Strong preference for stakeholder engagement through workshops and dissemination activities.

Grant Details